1. Field of Invention
This invention pertains generally to semiconductor memory devices and, more particularly, to a self-aligned split-gate flash memory and process of fabricating the same.
2. Related Art
Nonvolatile memory is currently available in several forms, including electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash EEPROM. Flash memory has been widely used for high volume data storage in devices such as memory cards, personal digital assistants (PDA's), cellular phones, and MP3 players. Such applications require high density memory, with smaller cell size and reduced cost of manufacture.
In general, there are two basic types of nonvolatile memory cell structures: stack-gate and split-gate. The stack-gate flash memory cell usually has a bit line contact, a source region, a floating gate, and a control gate, with the control gate being positioned directly above the floating gate. In a split-gate cell the control gate is still positioned above the floating gate, but it is offset laterally from it. The fabrication process for a stack-gate cell is generally simpler than that for a split-gate cell. However, a stack-gate cell has an over-erase problem which a split-gate cell does not have. This problem is commonly addressed by maintaining the threshold voltage of the cell in a range of about 1.0-2.0 volts after an erase cycle, which adds complexity to the circuit design.
Although a split-gate memory cell has no over erase problem, it generally includes an additional gate known as a select gate. Such cells are typically fabricated in double-poly or triple-poly processes which involve relatively complex processing steps. In addition, split-gate cells are generally larger than stack-gate cells. Nevertheless, because of the relatively simple circuit design which is possible when there is no over-erase problem, split-gate cells are used widely, particularly in embedded nonvolatile memory applications.
FIG. 1 illustrates a split-gate, self-aligned flash memory cell 16 which is described in detail in U.S. Pat. No. 6,091,104. This cell has a silicon substrate 17, with drain and source regions 18, 19 formed in a channel region 21. A floating gate 22 and a control gate 23 are formed above the channel region, with a gate oxide 24 between the substrate and the floating gate, and a dielectric film 26 between the floating gate and the control gate. A select gate 27 is formed to one side of the floating gate and control gate, with an oxide layer 28 between the select gate and the substrate, a dielectric film 29 between the select gate and the control gate, and another dielectric film 30 between select gate and the floating gate.
In the program mode, control gate 23 is biased at a high positive voltage (e.g., 10-12 volts), the source at another high positive voltage (e.g., 6-8 volts), select gate at a lower positive voltage (e.g., 1-2 volts), and the drain at 0 volts. This establishes an electric field across off-gate channel region 25 between the floating gate and select gate, which initiates hot electron injection, with electrons migrating from the channel region to the floating gate.
In one erase mode, a negative voltage of about −10 volts is applied to control gate, a positive voltage of about 7 volts is applied to the select gate, and the source and drain are left floating. The strong electric field thus created across inter-poly dielectric film 30 initiates Fowler-Nordheim tunneling, with electrons migrating from the floating gate to the select gate. In another erase mode, a negative voltage of about −10 volts is applied to control gate, a positive voltage of about 7 volts is applied to the source, and the drain and select gate are left floating. The strong electric field thus created across gate oxide 24 initiates Fowler-Nordheim tunneling, with electrons migrating from the floating gate to the source.
As fabrication processes improve and geometries get smaller, e.g. tens of nanometers, it is difficult to form a high-voltage coupling ratio which is sufficient for program and erase operations while keeping cell size small and meeting stringent reliability requirements such as 10-year data retention and 1,000,000 cycling operations between failures.